This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 60/706,421, filed on Aug. 9, 2005, the entire contents of which are hereby incorporated by reference herein.
1. Field of the Invention
The present invention relates to systems for communicating data via a communication channel. More particularly, the present invention relates to a cascode gain boosting system and method that can be used in a transmitter, such as, for example, a gigabit transmitter or the like.
2. Background Information
For purposes of illustration, FIG. 1 is a diagram illustrating a transmission system 100 that can be used to transmit, for example, a differential output current signal IOUT. In differential mode, IOUT=IOUT+−IOUT−. In the differential configuration, the transmission system 100 includes a driver circuit 103 for a first polarity signal configured to generate the positive component signal (e.g., IOUT+) of the differential output current signal. A driver circuit 107 for a second polarity signal is configured to generate the negative component signal (e.g., IOUT−) of the differential output current signal. The driver circuit 103 for the first polarity signal and the driver circuit 107 for the second polarity signal are respectively coupled to an interface circuit 150 for interfacing the driver circuits to unshielded twisted pairs (hereinafter “UTP”) 155 (e.g., Category-5 twisted pair cables for a gigabit channel or the like). The interface circuit 150 can include one or more resistors RTX. The resistor RTX is arranged in parallel across the primary windings of an isolation transformer 165, with the secondary windings coupled to the UTP 155. The isolation transformer 165 includes a center tap on the primary windings with a DC center tap voltage, VCT 170.
The driver circuit 103 for the first polarity signal includes a pair of transistors (e.g., first transistor Q1 and second transistor Q2) arranged in a cascode configuration. In such a cascode circuit, the first transistor Q1 is arranged in a common-source (or common-emitter) configuration, and is followed by the second transistor Q2 arranged in a common-gate (or common-base) configuration that is biased by a (constant) bias voltage, such as, for example, bias signal VBIAS. The bias signal VBIAS can be operated at a value determined by, for example, the saturation condition of the transistors at the maximum output current.
More particularly, the first transistor Q1 includes a gate electrode configured to receive an input signal VINPUT, and a source electrode coupled to a reference voltage 130 (e.g., a ground) through a load (e.g., source resistor RS+). The second transistor Q2 includes a gate electrode configured to receive the bias signal VBIAS, and a source electrode coupled to the drain electrode of the first transistor Q1. The positive component signal of the differential output current signal (e.g., IOUT+) is output on the drain electrode of the second transistor Q2, which is coupled to the interface circuit 150. For purposes of illustration, denote the gain of the first transistor Q1 as A1, and the gain of the second transistor Q2 as A2. Consequently, the output impedance RO+ of the driver circuit 103 for the first polarity signal (i.e., the output impedance looking “down” into the driver circuit 103 for the first polarity signal) is given as: RO+=(A1)(A2)RS+. The driver circuit 107 for the second polarity signal comprises a similar configuration and operation to that of the driver circuit 103 for the first polarity signal to output the negative component signal of the differential output current signal (e.g., IOUT−).
With respect to the driver circuit 103 for the first polarity signal, the input signal VINPUT is applied to the gate electrode of the first transistor Q1, and the bias signal VBIAS is applied to the gate electrode of the second transistor Q2. The first transistor Q1 converts the input signal VINPUT into a proportional current, which produces potential variations on the source electrode of the second transistor Q2. These variations appear on the output of the driver circuit 103 for the first polarity signal, amplified by the gain factor of the first and second transistors Q1 and Q2. The cascode configuration can operate, for example, to keep the current at node 140 (located between the drain electrode of the first transistor Q1 and the source electrode of the second transistor Q2) substantially constant so that there is little signal sweep, and, therefore, little change in the current output by the first transistor Q1. However, in the presence of very large swings of the output signals, lowering the center tap voltage VCT 170 can move the cascode circuit closer to its swing point. For purposes of illustration, let VCT=1.8 V. For 10 BASE-T operation, VTX+=VCT±1.25 V. Thus, the output voltage (VTX+) of the driver circuit 103 for the first polarity signal can swing from 0.55 V to 3.05 V. However, the lower swing voltage of 0.55V can result in the “quashing” of the second transistor Q2 and pushing the first transistor Q1 into saturation and out of its corresponding linear operating range.
Therefore, there is a need for an improved transmitter design to allow transmission systems, such as, for example, transmission system 100, to operate at very low center tap voltages.